(1) Field of the Invention
The present invention relates to an interleaving memory which enables a high-speed-data-output.
(2) Description of the Related Arts
A high-speed data processing such that meets today's need necessitates a high-speed-memory-readout which is by no means easy to realize; for it unavoidably takes a certain time, or a cycle time (Tc) for memory access.
Given these circumstances, a method called interleaving was proposed. A memory employing this method, a so-called interleaving memory, consists of n data banks so that the access width thereof becomes n times as wide as that of a data bus to reduce Tc to Tc/n, thereby increasing the memory-readout speed for sequential addressing [for further information, see "Handbook of Electric Data Transmission", page 1667, 1988, Ohm-sha].
Depicted in FIG. 1 are an interleaving memory for 2-way and a calculator. The interleaving memory comprises a first memory 301 and a second memory 302, each consisting of a 0-bank and a 1-bank which store data at even-numbered addresses and odd-numbered addresses respectively. A calculator 303 carries out arithmetic logic operations (hereinafter, simply referred to as arithmetic operations) of data inputted thereto from the first memory 301 by way of a first bus 304, and from the second memory 302 by way of a second bus 305.
With the first memory 301, data are read out from the 0-bank and 1-bank in the same Tc's, and inputted into the first bus 304 sequentially. For example, when address 2n is assigned as a starting address, data at address 2n and the following address 2n+1 are read out in the same Tc; the former are inputted into the first bus 304, and the latter are done so immediately without being read out when address 2n+1 is assigned subsequently, thereby reducing Tc and hence the memory-readout time by half. With the second memory 302, data are read out and inputted into the second bus 305 synchronously with the first memory 301 in the same manner. As a result, data at contiguous addresses are steadily inputted from each memory into the calculator 303 twice as fast as non-interleaving memories, the illustration of which is shown in FIG. 2.
Data at even-numbered addresses--2n, 2n+2, 2n+4, . . . --are steadily read out from the 0-bank of the first memory 301, while those at odd-numbered addresses--2n+1, 2n+3, 2n+5, . . . --from the 1-bank. Thus, the addresses of data read out in the same Tc's are: (2n, 2n+1), (2n+2, 2n+3), (2n+4, 2n+5), (2n+6, 2n+7), (2n+8, 2n+9), . . .
Synchronously, data at even-numbered addresses--2m, 2m+2, 2m+4, . . . --are steadily read out from the 0-bank of the second memory 302, while those at odd-numbered addresses 2m+1, 2m+3, 2m+5, . . . --from the 1-bank. Thus, the addresses of data read out in the same Tc's are : (2m, 2m+1), (2m+2, 2m+3), (2m+4, 2m+5), (2m+6, 2m+7), (2m+8, 2m+9), . . .
As previously explained, these data are inputted into the calculator 303 consecutively by way of the first bus 304 and second bus 305 in half a time. Thus, the calculator 303 carries out arithmetic operations of data at addressess: (2n, 2m), (2n+1, 2m+1), (2n+2, 2m+2), (2n+3, 2m+3), . . . twice as fast as the non-interleaving memories. In other words, the interleaving memory makes it possible to increase the memory-readout speed hence data processing speed twice as fast.
However, interleaving is effective only for arithmetic operations of data read out from each memory in the same Tc's; otherwise the effects are eliminated as will be explained with referring to FIG. 3.
The data are inputted into the calculator 303 consecutively in the same manner as explained in the above, but the calculator 303 carries out arithmetic operations of data at addresses: (2n, 2m+1), (2n+1, 2m+2), (2n+2, 2m+3), . . . Obviously, not all the data at addresses in brackets are read out in the same Tc's. For example, data at addresses (2n, 2m+1) are read out in the same Tc, but are not the data at the following addresses (2n+1, 2m+2); data at address 2m+2 are read out one Tc behind those at address 2n+1. Therefore, in every other operation, data from the second memory 302 have not been read out when the calculator 303 is to carry out the arithmetic operation. For this reason, calculator 303 can carry out only one arithmetic operation per Tc as do the non-interleaving memories, thereby utterly eliminating the effects of interleaving.
Given these circumstances, an interleaving memory such that can increase the memory-readout speed hence data processing speed even when data used for the arithmetic operations are read out in different Tc's has been sought after.